1. Field of the Invention
The present invention relates to a nonvolatile (e.g., flash) memory device. More specifically, the present invention relates to a NOR-type flash memory cell array structure and a method for manufacturing the same.
2. Description of the Related Art
A flash memory is a kind of PROM (programmable ROM) capable of electrically re-writing data. The flash memory can perform a program input scheme of an erasable PROM (EPROM) and an erase scheme of an electrically erasable PROM (EEPROM) using one transistor by combining the advantages of an EPROM, in which a memory cell includes one transistor so that a cell area is small, but data must be erased at a time by UV rays, and the EEPROM, in which data can be electrically erased, but the cell may include two transistors so that a cell area becomes large. Flash memory may also be known as flash EEPROM. Such a flash memory is referred to as a nonvolatile memory since stored information is not erased even though power is turned off, which is different from a dynamic RAM (DRAM) or a static RAM (SRAM).
Flash memory may be classified into a NOR-type structure in which cells are arranged in parallel between a bit line and a ground and a NAND-type structure in which cells are serially arranged between the bit line and the ground. Since the NOR-type flash memory having the parallel structure can perform high-speed random access when a reading operation is performed, the NOR-type flash memory is widely used for booting a mobile telephone. The NAND-type flash memory having the serial structure has low reading speed but high writing speed so that the NAND-type flash memory is suitable for storing data and is advantageous for miniaturization.
In addition, the flash memory can be classified into a stack gate type and a split gate type in accordance with the structure of a unit cell, and can be similarly classified into a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device in accordance with the shape and/or materials of a charge storage layer. Among them, the floating gate device includes floating gates having polycrystalline silicon and being surrounded by an insulating substance. Charges are implanted into or discharged from the floating gates by channel hot carrier injection or Fowler-Nordheim (F-N) tunneling so that data can be stored and erased.
Meanwhile, in the procedure of manufacturing the NOR type flash memory device, a cell threshold voltage is adjusted, and a stack gate including a floating gate, an inter-gate insulating layer (e.g., Oxide-Nitride-Oxide) and a control gate is formed. In addition, a common source line is formed through a self-aligned source (SAS) process. The SAS technique is used for reducing a cell size in a word-line direction. According to SAS technique, a common source line is formed through a dopant implantation process after etching a field oxide layer on the basis of etching selectivity among a polysilicon layer for a gate electrode, a silicon substrate, and a field oxide layer.
Recently, as the high integration and the high speed of a device are accelerated, it is necessary to design a smaller memory cell and a resistor having lower resistance. However, a manufacturing process of a conventional NOR-type cell structure may have some problems. For example, when an SAS process is performed in order to form a common source line, the unevenness or topology of an SAS line can cause an increase in resistance. This becomes a factor of reducing an operational speed of the device. In addition, the limitation of a photo process makes it difficult to control a line width of a control gate, so voids may be created due to the lack of a gap-fill margin when a polysilicon metal dielectric (PMD) layer is deposited on a drain area. Accordingly, when a tungsten plug is formed in the drain area, there may occur a short between a control gate and a bit line.